1. Technical Field
The present invention relates to a clock switching circuit.
2. Related Art
For example, in the case of a selector that receives a plurality of clocks and outputs one of the plurality of clocks according to a switching signal, there may arise a clock pulse, which has a narrow pulse width and is called a hazard, at the time of switching from one clock to another clock. There is a chance of such a hazard to come up when, for example, a switching signal is set to be active in order to implement clock switching while one clock is at a high level and the other clock is at a low level. Such a phenomenon is caused by delay of the switching signal in the selector. Since the hazard may result in a chance of causing mis-operation and so on of other circuits, it is needed to implement clock switching in a period while both the one clock and the other clock are together at their high level or low level, for the purpose of preventing any such a hazard. Consequently, it is impossible for a conventional clock switching circuit to carry out clock switching within a short time.
Also there is another type of clock switching circuit developed for the purpose of preventing such a hazard by another method (Japanese Unexamined Patent Publication No. JP8107406). A clock switching circuit described in JP8107406 is configured in such a manner that the output of one clock gets stopped at the time of clock switching and then the other clock is output after a certain time has passed by.
Though conventional clock switching circuits including the one described in JP8107406 are able to prevent any such a hazard from arising, they are accompanied by a problem that time for clock switching becomes longer.
The present invention has been developed in view of the technical problem described above, and the objective of the present invention is to provide a clock switching circuit that can carry out clock switching at an earlier timing without causing any hazard.